This application claims the priority benefit of Taiwan application serial no. 89114317, filed Jul. 18, 2000.
1. Field of Invention
The present invention relates to a regulated-cascode amplifier circuit. More particularly, the present invention relates to a regulated-cascode amplifier with a clamping circuit.
2. Description of Related Art
In conventional technique, the gain of an amplifier is increased by increasing the resistance of output load. One method of increasing load resistance of an amplifier is to use cascode transistors to serve as an output load. A cascode transistor load is formed by connecting a common source metal-oxide-semiconductor (MOS) transistor and a common gate MOS transistor serially. Another method of increasing load resistance of an amplifier is to use an auxiliary amplifier to generate an even higher load in addition to a cascode transistor load. This type of special circuit architecture is referred to as a regulated-cascode load.
However, when output signal from an amplifier having the regulated-cascode load is amplified to the largest possible value, the amplifier and the auxiliary amplifier may have to operate in their respective non-linear operating region. Once the amplifiers are operating in a non-linear operating region, signal will take longer to recover than when the amplifiers are operating in the linear operating region. Therefore, signal sampled after the amplifiers have stepped into the non-linear operating region will be distorted.
Because the auxiliary amplifier in a regulated-cascode amplifier circuit increases pole-zero, settling speed of the amplifier will be affected. In conventional technique, a compensation capacitor is generally added to the output terminal of the auxiliary amplifier. FIG. 1 is a circuit diagram showing a conventional regulated-cascode amplifier circuit. As shown in FIG. 1, output terminals 144a and 144b of an auxiliary amplifier 140 are connected to compensation capacitors 146a and 146b respectively. Similarly, output terminals 154a and 154b of an auxiliary amplifier 150 are connected to compensation capacitors 156a and 156b respectively. When a large positive signal-swing input and turns off gate 116a, the feedback-loops (152a, 154b, 114a, 132b) and (142b, 144b, 112b, 130b) in branch 104 are broken respectively. The output of the auxiliary amplifiers 140 and 150 are driven the largest possible value. Under this condition, both the main-amplifier and the auxiliary amplifiers will run into the nonlinear region with slow settling behavior. The same behavior happened at the opposite branch 102 and large negative input signal. The recovery speed with this type of circuit architecture is limited by the slew rates of the auxiliary amplifiers 140 and 150. Since the tail current of an auxiliary amplifier is small, recovery speed of the amplifier is rather slow. Therefore, to have a higher recovery speed for the amplifier, the tail current of the auxiliary amplifiers 140 and 150 needs to be increased. However, increasing the tail current tends to increase power consumption of the circuit. In addition, maximum increase in the tail current is ultimately constrained by unit-gain frequency related stability of the auxiliary amplifier.
In brief, conventional treatment of regulated-cascode amplifier often leads to a slow-down of processing speed. Moreover, once the amplifier moves into the nonlinear operating region, recovery speed is retarded. At present, the only effective method of boosting speed is to increase the level of power consumption.
Accordingly, one object of the present invention is to provide a regulated-cascode amplifier having a clamping circuit therein. The clamped regulated-cascode amplifier circuit includes a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and their corresponding clamping circuits. The positive sub-line and the negative sub-line are connected to a positive voltage supply line and a negative voltage supply line. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. Each positive sub-line and negative sub-line has a cascode transistor structure. Each cascode transistor structure includes at least a first cascode transistor and a second cascode transistor connected to their corresponding output terminals and the positive voltage supply line. In addition, each cascode transistor structure also includes at least a third cascode transistor and a fourth cascode transistor connected to their corresponding output terminal the negative voltage supply line. Furthermore, the source/drain terminals of the first cascode transistor are connected to the positive voltage supply line and a first voltage point. The source/drain terminals of the second cascode transistor are connected to the first voltage point and the corresponding output terminal. The source/drain terminals of the third cascode transistor are connected to the negative voltage supply line and a second voltage point. The source/drain terminals of the fourth cascode transistor are connected to the second voltage point and the corresponding output terminal.
The first auxiliary amplifier and the second auxiliary amplifier each has a positive terminal and a negative terminal, a positive-bias output terminal and a negative-bias output terminal. The input terminals of the first auxiliary amplifier are coupled to the first voltage point of the positive sub-line and the negative sub-line respectively. The input terminals of the second auxiliary amplifier are coupled to the second voltage point of the positive sub-line and the negative sub-line respectively. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. The first auxiliary amplifier and the second auxiliary amplifier each contains the aforementioned clamping circuit. The positive-bias output terminal and the negative-bias output terminal of each auxiliary amplifier is connected to the terminals of their corresponding diodes in their respective clamping circuit.
In brief, the invention utilizes the connection between the output terminal of an auxiliary amplifier with a clamping circuit comprising of two front-to-end connected diodes so that the amplifier always operates in the linear region. With such an arrangement, operating speed of the regulated-cascode amplifier is increased without a corresponding increase in power consumption.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.